The present invention relates to data processing circuits with a limited size (e.g. 16-bit) instruction register and a limited number of operation codes (e.g., 64 six-bit codes), and to techniques for expanding the instruction set.
U.S. Pat. No. 5,440,701 to Matsuzaki et al. disclose a data processing apparatus in which an instruction having an operation code (4-, 6- and 8-bits) and two register designation codes is decoded, and in some cases the instruction execution device executes a first process when the register designation codes are different but executes a second process when the register designation codes are equal.
U.S. Pat. No. 5,568,624 to Sites et al. disclose a RISC processor having a fixed (32-bit) instruction size with 6-bit operation codes in which a limited instruction set, permitting only simplified memory access data width and addressing modes, includes byte manipulation instructions, non-aligned load and store instructions, and load/locked and store/conditional instructions for implementing atomic byte writes.
Normally, each type of instruction requires its own operation code, and different addressing modes, special data formats (e.g. byte, half-word, word), and the presence of immediate data are indicated with different operation codes. However, in a Reduced Instruction Set Computer, RISC, processor, the number of operation code, op code, instructions is limited, and only the most basic op code instructions are included.
It is an objective of the invention to expand the number of operations, i.e., the instruction set, of a RISC processor, without adding more op code instructions to its official op code list.
It is another object of the present invention to expand the operations of existing op code instructions to handle immediate data, byte and half-word load and store operations and indexed-addressed load, store and jump operations.
The objective is met by employing special registers codes to designate the additional operations. For example, when certain operations, such as ADD or MOV, are applied to these special registers, the processor""s response to these op code instructions will be modified to use immediate data following in the next instruction word. Thus, if the register code for a special general register is found in the instruction""s source register code field, the register itself may be ignored and the processor may wait for substitute immediate data expected in one or more extended words. In certain memory reference operations, such as load, store or jump, the code for a special general register in the instruction""s source register field is used to indicate that these registers are to be used as base or index registers for indexed addressing. Still other special register codes may mean that a load or store operation is to be executed as byte (8-bit) or half-word (16-bit), instead of word (32-bit), memory transfers. When the special register codes are used with any other op code instruction not predefined to have additional functionality, the special general register will behave like any other non-special general register. Similarly, when a non-special register is used, in a special op code instruction with extended functionality, the non-special register is interpreted as a normal general purpose registers containing operand data or direct memory addresses.
The use of these special register codes has been found to not significantly reduce the availability of general purpose registers, while providing multiple functionality to certain operation code instruction, thereby extending the available number of operations without expanding the size of the op code instruction size.